1. Field of the Invention
The present invention relates to a process error prevention method in semiconductor fabricating equipment. More particularly, the present invention relates to a method for preventing process errors by controllably releasing interlocks when process parameters are input beyond set values and interlocks are generated at a rate exceeding a predetermined frequency, i.e., when a count of interlock occurrences exceeds a predetermined number within a predetermined period of time.
2. Description of the Related Art
In order to fabricate a semiconductor device, wafers are repeatedly subjected to a set of processes, such as cleaning, diffusion, photoresist coating, exposure, developing, etching, ion implantation, and the like. Specialized equipment is used for performing each of these processes. In order to optimize a fabrication line, wafers are typically processed in batches, or lots, of about 20 to 25 wafers.
Quality control parameters are typically created during each of the processes and are communicated to processing equipment and control computers where the data is stored for subsequent analysis. After a typical process is completed, a measuring process is performed to determine whether defective wafers have been created in the process. If defective wafers are detected, an interlock operation is activated to halt further processing activity, and an alarm signal is generated to alert a process operator.
Upon confirming that the equipment is interlocked, the operator informs a skilled engineer regarding the interlocked state of the equipment. Upon learning of the interlock condition, the engineer takes a series of steps to resolve the problem that prompted the interlock. When informed that the problems have been resolved, the operator releases the interlock in the equipment, thereby enabling the equipment to resume the wafer processing.
Due to technological trends toward higher integration density, tighter design rules, and lower device operating voltages, however, data collection of parameter (DCOP), static process control and interlock referencing are subjected to quality control test tolerances that are tighter and more complex. In addition, double interlock capability may be included in the processing equipment.
Thus, interlock stoppages of equipment in a single process line may be generated hundreds of times per day. Further, frequent interlock occurrences may be created that are prompted by a recurring, uncorrected or insufficiently corrected error. Such interlock stoppages degrade productivity and may also cause massive defects in quality if other engineering personnel are not informed of an interlock generation activity and/or do not know that the interlocks are caused by a recurring problem. Such xe2x80x9crecurring errorxe2x80x9d interlocks may result from a problem that has been only temporarily repaired or xe2x80x9cmaskedxe2x80x9d by an erroneous repair solution whereupon the problem may later recur.
In an effort to solve the problems described above, it is a feature of an embodiment of the present invention to provide a process error prevention method for preventing multiple interlocks that may be prompted by a recurring error, e.g., a same cause, in a semiconductor fabricating process. An interlock that is created due to a predetermined number of interlock fault signals from a same processing station occurring within a predetermined period of time preferably causes a master interlock to occur, thereby inhibiting operation of the processing station. Interlock-release authority, being limited to only a few authorized skilled engineers, may be exercised only upon proper resolution and logging of the interlock fault condition.
In the description and claims of the present invention, the term xe2x80x9cthree-strike-out,xe2x80x9d as in xe2x80x9cthree-strike-out modulexe2x80x9d or xe2x80x9cthree-strike-out process,xe2x80x9d refers to an act of counting a number of times an event occurs and causing a piece of equipment that may be responsible for the occurrence of that event to be disabled when the number of times reaches a predetermined number, or a piece of equipment for performing the act above. The predetermined number is not necessarily three.
According to an embodiment of the present invention, a process error prevention method preferably includes: generating a plurality of manufacturing process characterization data signals in a plurality of pieces of semiconductor fabricating equipment; transmitting the process characterization data signals to a data collecting server; comparing in the data collecting server the process characterization data signals to a range of optimum process conditioning parameters that are stored in a database in the data collecting server; continuing the manufacturing process if the results of the comparisons satisfy an acceptance criteria; generating an interlock signal and transferring that interlock signal to a xe2x80x9cthree-strike-outxe2x80x9d module if the results of the comparisons do not satisfy the acceptance criteria; disabling a particular one of the plurality of pieces of semiconductor fabricating equipment via the three-strike-out module if associated interlocks are received in the three-strike-out module as many as a predetermined number of times within a predetermined period of time. This ensures that the piece of semiconductor fabricating equipment does not operate until authorized engineers resolve the acceptance criteria problem. Upon notification that the problem has been resolved, preferably only a restricted set of authorized personnel may cause resetting and/or re-enabling of both the particular piece of disabled semiconductor fabricating equipment and a related portion of the three-strike-out module. Preferably, re-enabling a disabled particular one of the plurality of pieces of semiconductor fabricating equipment occurs only upon an inputting of a correct authorization code.
In the process error prevention method of the present invention, the predetermined number is preferably set in the three-strike-out module, and the predetermined number is preferably three.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.